The invention relates to high frequency power semiconductor packages and the method of construction of such packages. Power transistor packages normally have a metallic flange brazed to the back of a circular ceramic carrier and the metallic flange is then mechanically attached to a large heat sink. The metallic flange can either be in the form of a threaded stud or a flat metallic body having through holes for mounting the metallic body to a heat sink. High frequency transistors have wide base, collector, and emitter leads in order to reduce any lead inductive effects and such leads are normally made as wide as possible.
The use of a metallic flange brazed to the bottom of the ceramic carrier makes power transistor packages bulky and unsuitable for use in hybrid assemblies.
The term hybrid assemblies as used herein refers to conductively and resistively metalized substrates (normally ceramic) to which transistor packages as well as other components are mounted to form a compact electronic module.
High power transistor dice are normally not directly mounted on the hybrid substrate because the substrate does not have a sufficiently high thermal conductivity and for repairability considerations. The large wide leads of high frequency packages waste space in hybrid assemblies and/or result in secondary lead cutting operations being necessitated. The wide external transistor leads also result in a large amount of gold being used since all external transistor leads are usually gold plated.
The normally used method of manufacturing high frequency power transistor packages consists of metalizing a circular ceramic package such that the top metalized layer is substantially gold, and bonding a gold plated kovar lead frame to the metalized areas on the ceramic carrier, usually with the use of a preform to insure a good bond. The individual transistor packages are then isolated from the lead frame and subsequently semiconductor dice are mounted and individually electrically tested. Thus individual handling of transistor packages before electrical testing is required. Also several individual components of the transistor package are separately metalized with gold before final assembly of the package. Gold is used because; it forms a eutectic with silicon to aid in mounting silicon semiconductor dice, it is compatible with present wire bonding techniques, and it provides a solderable non-corroding coating for the external leads.